Semiconductor memory device and method for manufacturing the same

ABSTRACT

A semiconductor memory device has a semiconductor substrate, a plurality of word lines formed at predetermined intervals on the semiconductor substrate, each word line having a gate insulating film, a charge storage layer, a first insulating film, and a controlling gate electrode which are stacked in order, and including a metal oxide layer above the level of the gate insulating film, a second insulating film covering a side of the word line and a surface of the semiconductor substrate between the word lines, and having a film thickness of 15 nm or less, and a third insulating film formed between the word lines adjacent to each other such that a region below the level of the metal oxide layer has a cavity.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority fromthe Japanese Patent Application No. 2008-44481, filed on Feb. 26, 2008,the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

The present invention relates to a semiconductor memory device and amethod for manufacturing the same.

In conventional nonvolatile semiconductor memory devices, a placebetween word lines thereof is filled in with an oxide or nitride film,the word line having a tunnel oxide film, a floating gate electrode, aninterpoly insulating film, and a controlling gate electrode which arestacked in order. However, an interval between word lines is shorten aselements are miniaturized, and therefore the conventional devices haveproblems as follows: increased variations in a threshold voltage of itsfloating gate due to a parasitic capacitance produced between thefloating gate electrodes of adjacent word lines thereof; and reducedwriting speed due to parasitic capacitances produced between theadjacent word lines and between the floating gate and diffusion layer.Moreover, it has a problem that a high electric field applied betweenthe electrodes destroys a buried material between the electrodes.

In order to solve such problems, it has been proposed to provide an airgap (a cavity) between word lines. For example, known is a method forforming an air gap by conducting an ashing process to remove asacrificial film with organic materials as a sacrificial film (e.g. seeJapanese Patent Laid-Open No. 01-137651). However, the method has aproblem that, when such a method is applied to formation of an air gapbetween word lines, carbons and the like contained in organic materialscauses the tunnel oxide film to be deteriorated.

Also, known is a method for stacking an oxide film with poor filling-incharacteristics on word lines and between the word lines and thenproviding a void between adjacent floating gate electrodes (e.g. seeU.S. Patent Application Publication No. 2006/0001073). However, such amethod has problems that variations in position and shape of the voidsoccur as well as variations in a threshold voltage for each cell occur,thereby decreasing reliability thereof.

Thus, the conventional method for forming an air gap has the problems ofdecreasing reliability of a semiconductor memory device.

SUMMARY OF THE INVENTION

According to one aspect of the present invention, there is provided asemiconductor memory device, comprising:

a semiconductor substrate;

a plurality of word lines formed at predetermined intervals on thesemiconductor substrate, each word line having a gate insulating film, acharge storage layer, a first insulating film, and a controlling gateelectrode which are stacked in order, and including a metal oxide layerabove the level of the gate insulating film;

a second insulating film covering a side of the word line and a surfaceof the semiconductor substrate between the word lines, and having a filmthickness of 15 nm or less; and

a third insulating film formed between the word lines adjacent to eachother such that a region below the level of the metal oxide layer has acavity.

According to one aspect of the present invention, there is provided amethod for manufacturing a semiconductor memory device, comprising:

forming a plurality of word lines at predetermined intervals on asemiconductor substrate, each having a gate insulating film, a chargestorage layer, a first insulating film, and a controlling gate electrodewhich are stacked in order, and including a metal oxide layer above thelevel of the gate insulating film;

forming a second insulating film having a film thickness of 15 nm orless so as to cover a side of the word line and a surface of thesemiconductor substrate between the word lines; and

forming a third insulating film so as to cover the word lines and aplace between the word lines using a CVD technique.

According to one aspect of the present invention, there is provided amethod for manufacturing a semiconductor memory device, comprising:

forming a first insulating film on a semiconductor substrate;

forming a first electrode layer on the first insulating film;

forming a trench formed at predetermined intervals along a firstdirection by etching the first electrode layer, the first insulatingfilm, and the semiconductor substrate;

forming an element isolating insulating film so as to fill in thetrench;

forming a second insulating film including a metal oxide layer on thefirst electrode layer and the element isolating insulating film;

forming a second electrode layer on the second insulating film;

forming a third insulating film on the second electrode layer;

forming word lines formed at predetermined intervals along a seconddirection perpendicular to the first direction by removing the thirdinsulating film, the second electrode layer, the second insulating film,the first electrode layer, the first insulating film, and the elementisolating insulating film so as to expose a surface of the semiconductorsubstrate;

forming a fourth insulating layer having a film thickness of 15 nm orless on a side of the word line and the surface of the semiconductorsubstrate between the word lines; and

forming a fifth insulating film using a CVD technique so as to cover theword line and a place between the word lines.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross sectional view of a process for explaining a methodfor manufacturing a semiconductor memory device according to a firstembodiment of the present invention;

FIG. 2 is a cross sectional view subsequent to FIG. 1;

FIG. 3 is a cross sectional view subsequent to FIG. 2;

FIG. 4 is a cross sectional view of a process for explaining a methodfor manufacturing a semiconductor memory device according to a secondembodiment of the present invention;

FIG. 5 is a cross sectional view subsequent to FIG. 4;

FIG. 6 is a cross sectional view subsequent to FIG. 5;

FIG. 7 is a cross sectional view of a process for explaining a methodfor manufacturing a semiconductor memory device according to a thirdembodiment of the present invention;

FIG. 8 is a cross sectional view subsequent to FIG. 7;

FIG. 9 is a cross sectional view subsequent to FIG. 8;

FIG. 10 is a schematic view of a semiconductor memory device accordingto a modification;

FIG. 11 is a cross sectional view of a process for explaining a methodfor manufacturing a semiconductor memory device according to amodification;

FIG. 12 is a cross sectional view subsequent to FIG. 11;

FIG. 13 is a cross sectional view subsequent to FIG. 12; and

FIG. 14 is a schematic view of a semiconductor memory device accordingto a modification.

DESCRIPTION OF THE INVENTION

Embodiments of the present invention will be described below withreference to drawings.

First Embodiment

FIGS. 1 to 3 show cross sectional views of a process for explaining amethod for manufacturing a semiconductor memory device according to afirst embodiment of the present invention. Each view shows a verticalsection along the direction of bit line in a memory cell array.

As shown in FIG. 1, a tunnel oxide film (a gate insulating film) 102composed of a silicon oxide film and a floating gate electrode 103composed of a polysilicon film are formed on a semiconductor substrate101.

A trench (not shown) is formed at predetermined intervals along apredetermined direction (the direction of bit line) by removing thefloating gate electrode 103, the tunnel oxide film 102, and thesemiconductor substrate 101. The trench is filled in with a siliconoxide film to a predetermined height to form an element isolating region(not shown). An upper surface of the element isolating region may belower than an upper surface of the floating gate electrode 103.

An interpoly insulating film 104 is formed so as to cover the floatinggate electrode 103 and the element isolating region. The interpolyinsulating film 104 includes a metal oxide. As the metal oxide, forexample, a Zr-based oxide such as ZrO₂, PbZrO₂, and BaZrO₃; a Hf-basedoxide such as HfO₂, HfON, and HfAlO; a La-based oxide such as LaO₃; anAl-based oxide such as Al₂O₃ and AlZrO₅; a Ta-based oxide such as Ta₂O₅;a Ti-based oxide such as TiO₂; and/or an Y-based oxide such as Y₂O₃ maybe used.

The interpoly insulating film 104, for example, may be a structure witha nitride film/an oxide film/a metal oxide/an oxide film/a nitride filmstacked.

A first polysilicon film is formed on the interpoly insulating film 104.A groove is formed by removing a part of the first polysilicon film andthe interpoly insulating film 104 in a region where a selectiontransistor and a peripheral transistor (both are not shown) will beformed. A second polysilicon film is formed on the first polysiliconfilm so as to fill in the groove.

In the memory cell array, a controlling gate electrode 105 is composedof the first polysilicon film and the second polysilicon film. In theselection gate transistor and the peripheral transistor, each has anetching interpoly structure in which the polysilicon films (electrodelayers) above and below the interpoly insulating film 104 are connected.

A silicon nitride film 106, then, is formed on the controlling gateelectrode 105. Subsequently, resists 107 are formed on the siliconnitride film 106 and a patterning is performed so as to be formed instrips along a direction (the direction of word line) perpendicular tothe above predetermined direction at predetermined intervals.

As shown in FIG. 2, the silicon nitride film 106 is etched using RIE(reactive ion etching) process with the resist 107 as a mask. Then, theresist 107 is removed. Following this, the controlling gate electrode105, the interpoly insulating film 104, the floating gate electrode 103,and the tunnel oxide film 102 are removed using RIE with the siliconnitride film 106 as a mask to fabricate word lines WL and selectiontransistors (not shown). At this time, a part of the element isolatingregion (not shown) is also removed.

The word lines WL each have the tunnel oxide film 102, the floating gateelectrode 103, the interpoly insulating film 104, and the controllinggate electrode 105 which are stacked in order. In one word line WL, thetunnel oxide film 102 and the floating gate electrode 103, and theelement isolating region (not shown) are alternately formed, as well asthe interpoly insulating film 104 is formed in a strip on the floatinggate electrode 103 and the element isolating region.

Subsequently, a silicon oxynitride film 110 is formed using an ALD(Atomic Layer Deposition) technique so as to cover the word lines WL andthe semiconductor substrate 101. The silicon oxynitride film 110 is madeto have a film thickness of 15 nm or less. In order to prevent surfaceleakage, it is necessary to make sure to form an oxide film or the likeso as to cover the word lines. Because of this, the silicon oxynitridefilm 110 is formed.

As shown in FIG. 3, a sub-atmospheric thermal CVD (Chemical VaporDeposition) film 111 is formed. The sub-atmospheric thermal CVD film 111is formed e.g. in the presence of TEOS (tetraethoxysilane: Si(OC₂H₅)₄),O₃, and H₂O gas in a temperature range of 380 to 480° C. and a pressurerange of 500 to 650 Torr.

The interpoly insulating film 104 includes a metal oxide. In thevicinity of this metal oxide, dissociative adsorption of oxygenmolecules occurs, and thus activated oxygens promote reaction. Thisphenomenon is also referred to as catalytic effect.

This catalytic effect promotes chemical reaction (TEOS oxidation) of thesub-atmospheric thermal CVD film 111. In other words, in a location ofthe interpoly insulating film 104 including the metal oxide, the CVDfilm 111 is rapidly grown, and a place between the word lines WL isoccluded before its lower portion being filled in.

Therefore, a place between the word lines WL below the interpolyinsulating film 104, i.e. a place between the floating gate electrodes103 is not filled in, and thus a cavity 112 is formed.

Though the silicon oxynitride film 110 is on a side of the interpolyinsulating film 104, the silicon oxynitride film 110 has a filmthickness of 15 nm or less, and therefore the catalytic effect of themetal oxide included in the interpoly cinsulating film 104 may influencethe growth of the CVD film 111.

The cavity part provided between the floating gate electrodes 103 allowsa parasitic capacitance between the floating gate electrodes 103 to bereduced to improve its operating speed.

Moreover, the catalytic effect of the metal oxide included in theinterpoly insulating film 104 facilitate the growth of the CVD film 111to form the cavity 112, and therefore variations produced in positionand shape of the respective cavity 112 between the word lines WL can beminimized. Accordingly, the occurrence of variations in a thresholdvoltage for each cell can be prevented, and a reliable semiconductormemory device is obtained.

Second Embodiment

FIGS. 4 to 6 show cross sectional views of a process for explaining amethod for manufacturing a semiconductor memory device according to asecond embodiment of the present invention. Each view shows a verticalsection along the direction of bit line in a memory cell array.

As shown in FIG. 4, a tunnel oxide film 202 composed of a silicon oxidefilm, and a floating gate electrode 203 composed of a polysilicon filmare formed on a semiconductor substrate 201.

A trench (not shown) is formed at predetermined intervals along apredetermined direction (the direction of bit line) by removing thefloating gate electrode 203, the tunnel oxide film 202, and thesemiconductor substrate 201. The trench is filled in with a siliconoxide film to a predetermined height to form an element isolating region(not shown).

An interpoly insulating film 204 is formed so as to cover the floatinggate electrode 203 and the element isolating region.

A first polysilicon film is formed on the interpoly insulating film 204.A groove is formed by removing a part of the first polysilicon film andthe interpoly insulating film 204 in a region where a selectiontransistor and a peripheral transistor (both are not shown) will beformed. A second polysilicon film is formed on the first polysiliconfilm so as to fill in the groove.

In the memory cell array, a controlling gate electrode 205 is composedof the first polysilicon film and the second polysilicon film. In theselection gate transistor and the peripheral transistor, the controllinggate electrode 205 has an etching interpoly structure in which thepolysilicon films (electrode layers) above and below the interpolyinsulating film 204 are connected.

A metal oxide film 206 is formed on the controlling gate electrode 205using the ALD technique. As the metal oxide, for example, a Zr-basedoxide such as ZrO₂, PbZrO₂, and BaZrO₃; a Hf-based oxide such as HfO₂,HfON, and HfAlO; a La-based oxide such as LaO₃; an Al-based oxide suchas Al₂O₃ and AlZrO₅; a Ta-based oxide such as Ta₂O₅; a Ti-based oxidesuch as TiO₂; and/or an Y-based oxide such as Y₂O₃ may be used.

Subsequently, resists 207 are formed on the metal oxide film 206 and apatterning is performed so as to be formed in strips along a direction(the direction of word line) perpendicular to the above predetermineddirection at predetermined intervals.

As shown in FIG. 5, the metal oxide film 206, the controlling gateelectrode 205, the interpoly insulating film 204, the floating gateelectrode 203, and the tunnel oxide film 202 are removed using RIE withthe resist 207 as a mask to fabricate word lines WL and selectiontransistors (not shown). Then, the resists 207 are removed.

Subsequently, a silicon oxynitride film 208 is formed using the ALD(Atomic Layer Deposition) technique so as to cover the word lines WL andthe semiconductor substrate 201. The silicon oxynitride film 208 is madeto have a film thickness of 15 nm or less. The silicon oxynitride film208 is necessarily formed for preventing surface leakage.

As shown in FIG. 6, a sub-atmospheric thermal CVD film 209 is formed.The sub-atmospheric thermal CVD film 209 is formed e.g. in the presenceof TEOS, O₃, and H₂O gas in a temperature range of 380° C. to 480° C.and a pressure range of 500 to 650 Torr.

The catalytic effect of the metal oxide included in the metal oxide film206 promotes chemical reaction (TEOS oxidation) of the sub-atmosphericthermal CVD film 209. In other words, in a location of the metal oxidefilm 206, the CVD film 209 is rapidly grown.

Therefore, a place between the word lines WL below the metal oxide film206, i.e. a place between the controlling gate electrodes 205 and aplace between the floating gate electrodes 203 is not filled in, andthus a cavity 200 is formed.

Though the metal oxide film 206 is covered with the silicon oxynitridefilm 208, the film 208 has a film thickness of 15 nm or less, andtherefore the catalytic effect of the metal oxide may influence thegrowth of the CVD film 209.

The cavity part provided between the floating gate electrodes 203 allowsa parasitic capacitance between the floating gate electrodes 203 to bereduced to improve its operating speed.

The cavity part also exists between the controlling gate electrodes 205,and therefore a resistance to pressure with respect to a high electricfield applied between electrodes is improved, and this makes thesemiconductor memory device reliable.

Moreover, the catalytic effect of the metal oxide film 206 promotes thegrowth of the CVD film 209 to form the cavity 200, and thereforevariations produced in position and shape of the respective cavity 200between the word lines WL can be minimized. Accordingly, the occurrenceof variations in a threshold voltage for each cell can be prevented, andthis makes the semiconductor memory device reliable.

Third Embodiment

FIGS. 7 to 9 show a cross sectional view of a process for explaining amethod for manufacturing a semiconductor memory device according to athird embodiment of the present invention. In each view, referencecharacters (a) show a vertical section of a memory cell array along thedirection of bit line, and reference characters (b) show a verticalsection along the direction of word line.

As shown in FIG. 7, a tunnel oxide film 302 composed of a silicon oxidefilm is formed on a semiconductor substrate 301, and a floating gateelectrode 303 having a stacking structure with a polysilicon film 303 a,a metal oxide layer 303 b, and a polysilicon film 303 c is formed on thetunnel oxide film 302.

As the metal oxide layer 303 b, for example, a Zr-based oxide such asZrO₂, PbZrO₂, and BaZrO₃; a Hf-based oxide such as HfO₂, HfON, andHfAlO; a La-based oxide such as LaO₃; an Al-based oxide such as Al₂O₃and AlZrO₅; a Ta-based oxide such as Ta₂O₅; a Ti-based oxide such asTiO₂; and/or an Y-based oxide such as Y₂O₃ as the metal oxide may beused.

A trench is formed at predetermined intervals along the direction of bitline by removing the floating gate electrode 303, the tunnel oxide film302, and the semiconductor substrate 301. The trench is filled in with asilicon oxide film to a predetermined height to form an elementisolating region 304 whose upper surface is lower than an upper surfaceof the floating gate electrode 303.

An interpoly insulating film 305 is formed so as to cover the floatinggate electrode 303 and the element isolating region 304.

A first polysilicon film is formed on the interpoly insulating film 305.A groove is formed by removing a part of the first polysilicon film andthe interpoly insulating film 305 in a region where a selectiontransistor and a peripheral transistor (both are not shown) will beformed. A second polysilicon film is formed on the first polysiliconfilm so as to fill in the groove.

In the memory cell array, a controlling gate electrode 306 is composedof the first polysilicon film and the second polysilicon film. In theselection gate transistor and the peripheral transistor, the controllinggate electrode 306 has an etching interpoly structure in which thepolysilicon films (electrode layers) above and below the interpolyinsulating film 305 are connected.

A silicon nitride film 307, then, is formed on the controlling gateelectrode 306. Subsequently, resists 308 are formed on the siliconnitride film 307 and a patterning is performed so as to be formed instrips along the direction of word line at predetermined intervals.

As shown in FIG. 8, the silicon nitride film 307 is etched using RIE(reactive ion etching) process with the resist 308 as a mask. Then, theresist 308 is removed. Following this, the controlling gate electrode306, the interpoly insulating film 305, the floating gate electrode 303,and the tunnel oxide film 302 are removed using RIE with the siliconnitride film 307 as a mask to fabricate word lines WL and selectiontransistors (not shown). Further, an oxide film (not shown) forpreventing surface leakage is formed so as to cover the word lines WL.

As shown in FIG. 9, a part of the silicon oxide film in the elementisolating region 304 is removed with wet etching.

Subsequently, a sub-atmospheric thermal CVD film 311 is formed. Thesub-atmospheric thermal CVD film 311 is formed e.g. in the presence ofTEOS, O₃, and H₂O gas in a temperature range of 380° C. to 480° C. and apressure range of 500 to 650 Torr. The floating gate electrode 303includes a metal oxide layer 303 b. The catalytic effect of this metaloxide promotes chemical reaction (TEOS oxidation) of the sub-atmosphericthermal CVD film 311. In other words, in a location of the metal oxidelayer 303 b, the CVD film 311 is rapidly grown.

Therefore, a place between the word lines WL below the metal oxide layer303 b, i.e. a lower portion between the floating gate electrodes 303 isnot filled in, and thus a cavity 312 is formed.

The cavity part provided between the floating gate electrodes 303 allowsa parasitic capacitance between the floating gate electrodes 303 to bereduced to improve its operating speed. A cavity is also formed in theelement isolating region, and therefore a parasitic capacitance producedbetween the floating gate electrode and the substrate can also bereduced.

Moreover, the catalytic effect of the metal oxide layer 303 bfacilitates the growth of the CVD film 311 to form the cavity 312, andtherefore variations produced in position and shape of the respectivecavity 312 between the word lines WL can be minimized. Accordingly, theoccurrence of variations in a threshold voltage for each cell isprevented, and this makes a semiconductor memory device reliable.

Though the semiconductor memory device according to the above embodimenthas a stack-gate memory cell structure of a controlling gateelectrode/an interpoly insulating film/a floating gate electrode/atunnel oxide film, the present invention can be applied to a MONOSstructure as well.

In the case where the method for forming an air gap (a cavity) accordingto the above second embodiment is applied to a MONOS structure, asemiconductor memory device as shown in FIG. 10 is obtained.

A word line WL has a tunnel oxide film 401, a trap nitride film 402, aninterpoly insulating film (a high dielectric film) 403, a controllinggate electrode 404, and a metal oxide film 405 which are stacked inorder on a semiconductor substrate 400. The controlling gate electrode404 includes a metal film 404 a and a polysilicon film 404 b.

A silicon oxynitride film 406 for preventing surface leakage is formedwith a film thickness of 15 nm or less so as to cover the word lines WLand the semiconductor substrate between the word lines WL.

As described in the above embodiments, the catalytic effect of a metaloxide included in the metal oxide film 405 promotes chemical reaction(TEOS oxidation) of a sub-atmospheric thermal CVD film 407. In otherwords, in a location of the metal oxide film 405, the CVD film 407 israpidly grown, and a place between the word lines WL below the metaloxide film 405 is not filled in, resulting in a formation of a cavity408.

With a semiconductor memory device with such a MONOS structure, as withthe above second embodiment, its operating speed and its resistance topressure with respect to a high electric field is improved, this makesit reliable.

Also, forming an element isolating region of the semiconductor memorydevice with the MONOS structure into a cavity, by way of example, isdescribed with reference to FIGS. 11 to 13. As shown in FIG. 11, atunnel oxide film 502, a trap nitride film 503, a block film 504including a metal oxide (e.g. alumina), a controlling gate electrode 505composed of a metal (e.g. TiN) film 505 a and a polysilicon film 505 b,and a silicon nitride film 506 are formed in order on a semiconductorsubstrate 501. Then, resists 507 are formed on the silicon nitride film506 and lithographic processing is performed so as to be formed in astrip at predetermined intervals along the direction of bit line.

As shown in FIG. 12, the silicon nitride film 506 is etched using RIEprocess with the resist 507 as a mask, and the resist 507 is separated.Then, the controlling gate electrode 505, the block film 504, the trapnitride film 503, the tunnel oxide film 502, and the semiconductorsubstrate 501 are etched using RIE process with the silicon nitride film506 as a mask to form a trench.

As shown in FIG. 13, a sub-atmospheric thermal CVD film 508 is formed.The block film 504 includes a metal oxide. The catalytic effect of themetal oxide promotes chemical reaction (TEOS oxidation) of thesub-atmospheric thermal CVD film 508. In other words, in a location ofthe block film 504, the CVD film 508 is rapidly grown. Therefore, thetrench located below the block film 504 is not filled in, and thus acavity 509 is formed. The element isolating region thus may be formedinto a cavity.

Moreover, in the above third embodiment, the metal oxide layer is formedin the floating gate electrode, and however, as shown in FIG. 14, it maybe designed to be formed in a controlling gate electrode CG. Thecontrolling gate electrode CG has a stacking structure of a firstcontrolling gate electrode film, a metal oxide film, and a secondcontrolling gate electrode film. Between adjacent word lines WL, thisforms a cavity 600 between floating gate electrodes FG and between lowerportions of the controlling gate electrodes CG (the first controllinggate electrode films).

1. A semiconductor memory device, comprising: a semiconductor substrate;a plurality of word lines formed at predetermined intervals on thesemiconductor substrate, each word line having a gate insulating film, acharge storage layer, a first insulating film, and a controlling gateelectrode which are stacked in order, and including a metal oxide layerabove the level of the gate insulating film; a second insulating filmcovering a side of the word line and a surface of the semiconductorsubstrate between the word lines, and having a film thickness of 15 nmor less; and a third insulating film formed between the word linesadjacent to each other such that a region below the level of the metaloxide layer has a cavity.
 2. The semiconductor memory device accordingto claim 1, wherein the metal oxide layer is included in the firstinsulating film.
 3. The semiconductor memory device according to claim2, wherein the first insulating film includes a first nitride film, afirst oxide film, the metal oxide layer, a second oxide film, and asecond nitride film which are stacked in order.
 4. The semiconductormemory device according to claim 1, wherein the metal oxide layer isformed on the controlling gate electrode.
 5. The semiconductor memorydevice according to claim 1, wherein the controlling gate electrodeincludes a first controlling gate electrode film, the metal oxide layer,and a second controlling gate electrode film which are stacked in order.6. The semiconductor memory device according to claim 1, wherein thecharge storage layer includes a first charge storage film, the metaloxide layer, and a second charge storage film which are stacked inorder.
 7. The semiconductor memory device according to claim 6, whereinin the word line, the gate insulating film and the charge storage layer,and a second cavity are alternately formed below the first insulatingfilm.
 8. The semiconductor memory device according to claim 7, wherein alower surface of the first insulating film covering the second cavity islocated lower than an upper surface of the second charge storage filmand higher than the metal oxide layer.
 9. The semiconductor memorydevice according to claim 1, wherein the second insulating film is asilicon oxynitride film.
 10. The semiconductor memory device accordingto claim 1, wherein the metal oxide layer includes at least any one ofZrO₂, PbZrO₂, BaZrO₃, HfO₂, HfON, HfAlO, LaO₃, Al₂O₃, AIZrO₅, Ta₂O₅,TiO₂, and Y₂O₃. 11-20. (canceled)